1. Field of the Invention
This invention relates to a driving circuit for a liquid crystal display, and more particularly to a shift register employing an amorphous silicon thin film transistor.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) used as a display device for a television or a computer controls light transmittance of a liquid crystal using an electric field to thereby display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged to intersect each other. The liquid crystal cell is positioned at each area defined by intersections between the gate lines and the data lines. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each liquid crystal cell. Each of the pixel electrodes is connected, via source and drain terminals of a thin film transistor as a switching device, to one of the data lines. A gate terminal of the thin film transistor is connected to one of the gate lines.
The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel. The data driver applies a video signal to each data line whenever the scanning signal is applied to one of the gate lines. Thus, the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with a video signal for each liquid crystal cell, thereby displaying a picture.
In such a driving circuit, the gate driver generates a scanning signal for sequentially driving the gate lines using a shift register. The data driver generates a sampling signal for sequentially sampling video signals inputted from the exterior thereof by a specific unit using the shift register.
FIG. 1 is a block diagram showing a configuration of a general two-phase shift register.
Referring to FIG. 1, the shift register includes 1st to nth stages connected in cascade. The 1st to nth stages are commonly supplied with first and second clock signals C1 and C2 along with high-level and low-level driving voltages (not shown), and are supplied with a start pulse Vst or an output signal of the previous stage. The 1st stage outputs a first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1 and C2. The 2nd to nth stages output 2nd to nth output signals, respectively, in response to the output signal of the previous stage and the first and second clock signals C1 and C2. The 1st to nth stages have an identical circuit configuration, and sequentially shift a specific voltage of the start pulse Vst. The 1st to nth output signals Out1 to Outn are supplied with a scanning signal for sequentially driving the gate lines of the liquid crystal display panel, or with a sampling signal for sequentially sampling a video signal within the data driver.
FIG. 2 shows a detailed circuit configuration of one stage shown in FIG. 1.
In FIG. 2, the stage includes a fifth NMOS transistor T5 for outputting a first clock signal C1 to an output line under control of a Q node, a sixth NMOS transistor T6 for outputting a low-level driving voltage VSS under control of a QB node, and first to fourth NMOS transistors T1 to T4 for controlling the Q node and the QB node.
Such a stage is supplied with high-level and low-level voltages VDD and VSS, and with the start pulse Vst and the first and second clock signals C1 and C2. Herein, the second clock signal C2 is a signal in which a high-state voltage and a low-state voltage each having a predetermined pulse width are alternately supplied, whereas the first clock signal C1 is a signal having a voltage opposite to the second clock signal C2. A high state of the start pulse Vst is synchronized with a high state of the second clock signal C2. The start pulse Vst is a signal supplied from the exterior or an output signal of the previous stage.
Hereinafter, an operation procedure of the stage will be described with reference to driving waveforms shown in FIG. 3.
In an A period, the first NMOS transistor T1 is turned on by a high-state second clock signal C2 to thereby apply a high-state voltage of the start pulse Vst to the Q node, that is, to pre-charge it. The high-stage voltage pre-charged to the Q node turns on the fifth NMOS transistor T5 to thereby apply a low-state voltage of the first clock signal to the output line. At this time, the second NMOS transistor T2 also is turned on by the high-state second clock signal to thereby apply a high-level driving voltage VDD to the QB node. Then, the high-level driving voltage VDD supplied to the QB node turns on the sixth NMOS transistor T6 to thereby supply a low-level driving voltage VSS. Thus, in the A period, the output line of the stage outputs a low-state output signal OUT.
In a B period, the first NMOS transistor T1 is turned off by a low-state second clock signal C2 to thereby float the Q node into a high state. Thus, the fifth NMOS transistor T5 keeps a turn-on state. At this time, as a high-state voltage is supplied as the first clock signal C1, the floated Q node is boot-strapped by an affect of an internal capacitor Cgs provided between the gate and the drain of the fifth NMOS transistor T5 and a capacitor CB. Accordingly, a voltage at the Q node is further raised to keep the fifth NMOS transistor T5 turned on, thereby rapidly supplying a high-state voltage of the first clock signal C1 to the output line. Further, the Q node floated into a high state turns on the fourth NMOS transistor T4 and a high-state first clock signal C1 turns on the third NMOS transistor T3 to supply the low-level driving voltage VSS to the QB node, thereby turning off the sixth NMOS transistor T6. Thus, in the B period, the output line of the stage outputs a high-state output signal OUT.
In a C period, the first NMOS transistor T1 is turned on by a high-state second clock signal C2 to supply a low-state voltage of the start pulse Vst to the Q node, thereby turning off the fifth NMOS transistor T5. At this time, the second NMOS transistor T2 is turned on by a high-state second clock signal C2 to supply the high-level driving voltage VDD to the QB node, thereby turning on the sixth NMOS transistor T6 to output the low-level driving voltage VSS to the output line. At this time, the third NMOS transistor T3 is turned off by a low-stage first clock signal C1 and the fourth NMOS transistor T4 is turned off by the low-state Q node, thereby keeping the high-level driving voltage VDD at the QB node. Thus, in the C period, the output line of the stage outputs a low-state output signal OUT.
In a D period, the second NMOS transistor T2 is turned off by a low-state second clock signal C2 and the fourth NMOS transistor T4 is turned off by the low-state Q node, thereby floating the QB node with keeping the high-level driving voltage VDD supplied in the previous period C even though the third NMOS transistor T3 is turned on by a high-state first clock signal C1. Thus, the sixth NMOS transistor T6 keeps a turn-on state to thereby output the low-level driving voltage VSS to the output line. As a result, in the D period, the output line of the stage outputs a low-state output signal OUT.
In the remaining period, the C and D periods are alternately repeated, so that the output signal OUT of the stage continuously keeps a low state.
Recently, various attempts have been made to apply a polycrystalline silicon thin film transistor capable of directly forming a shift register on a glass substrate to an amorphous silicon thin film transistor. However, the amorphous silicon thin film transistor has a bias temperature stress characteristic in which it operates erroneously due to bias stress when a direct current (DC) voltage is continuously supplied to the gate terminal thereof in a high temperature operation.
In a conventional shift register, a DC-type high-level driving voltage VDD is applied to the QB node that is a gate node of the sixth NMOS transistor during a majority of period (i.e., during the remaining period other than 1H or 2H interval at which the Q node has a high state) as shown in FIG. 3. Accordingly, the conventional shift register has a problem in that, when it is operated at a high temperature, the sixth NMOS transistor T6 is erroneously operated due to gate bias stress.